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1 ? ha-5020 100mhz current feedback video amplifier with disable the ha-5020 is a wide bandwidth, high slew rate amplifier optimized for video applications and gains between 1 and 10. manufactured on intersil?s reduced feature complementary bipolar di proc ess, this amplifier uses current mode feedback to maintain higher bandwidth at a given gain than conventional voltage feedback amplifiers. since it is a closed loop devic e, the ha-5020 offers better gain accuracy and lower distortion than open loop buffers. the ha-5020 features low diff erential gain and phase and will drive two double terminated 75 ? coax cables to video levels with low distortion. adding a gain flatness performance of 0.1db makes this amplifier ideal for demanding video applications. the bandwidth and slew rate of the ha-5020 are relatively independent of closed loop gain. the 100mhz unity gain bandwidth only decreases to 60mhz at a gain of 10. the ha-5020 used in place of a conventional op amp will yield a significant improvement in the speed power product. to further reduce power, ha-5020 has a disable function which significantly reduces supply current, while forcing the output to a true high impedance state. this allows the outputs of multiple amplifiers to be wire-or?d into multiplexer c onfigurations. the device also includes output short circuit protection and output offset voltage adjustment. for multi channel versions of the ha-5020 see the ha5022 dual with disable, ha5023 dual, ha5013 triple and ha5024 quad with disable op amp data sheets. pinout ha-5020 (pdip, soic) top view features ? wide unity gain bandwidth . . . . . . . . . . . . . . . . . 100mhz ? slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800v/ s ? output current . . . . . . . . . . . . . . . . . . . . . . . 30ma (min) ? drives 3.5v into 75 ? ? differential gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% ? differential phase . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.03 ? low input voltage noise . . . . . . . . . . . . . . . . . 4.5nv/ hz ? low supply current . . . . . . . . . . . . . . . . . . . . 10ma (max) ? wide supply range . . . . . . . . . . . . . . . . . . . 5v to 15v ? output enable/disable ? high performance replacement for el2020 ? pb-free plus anneal available (rohs compliant) applications ? unity gain video/wideband buffer ? video gain block ? video distribution amp/coax cable driver ? flash a/d driver ? waveform generator output driver ? current to voltage converter; d/a output buffer ? radar systems ? imaging systems bal in- in+ v- 1 2 3 4 8 7 6 5 disable v+ out bal + - data sheet june 5, 2006 fn2845.11 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2002, 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn2845.11 june 5, 2006 ordering information part number part marking temp. range (c) package pkg. dwg. # ha3-5020-5 ha3-5020-5 0 to 75 8 ld pdip e8.3 ha3-5020-5z (note) ha3-5020-5z 0 to 75 8 ld pdip (pb-free) e8.3 ha9p5020-5 50205 0 to 75 8 ld soic m8.15 ha9p5020-5z (note) 50205z 0 to 75 8 ld soic (pb-free) m8.15 HA9P5020-5X96 50205 0 to 75 8 ld soic tape and reel m8.15 ha9p5020-5zx96 (note) 50205z 0 to 75 8 ld soic tape and reel (pb-free) m8.15 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ha-5020
3 fn2845.11 june 5, 2006 absolute maxi mum ratings (note 1) thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . 36v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10v output current . . . . . . . . . . . . . . . . . . . . . . . short circuit protected operating conditions temperature range ha-5020-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 75c thermal resistance (typical, note 2) ja (c/w) jc (c/w) pdip package . . . . . . . . . . . . . . . . . . . 120 n/a soic package . . . . . . . . . . . . . . . . . . . 165 n/a maximum junction temperature (plastic packages, note 1) . . . 150c maximum storage temperature range . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. maximum power dissipation, including output load, must be des igned to maintain junction temperature below 150c for plastic p ackages. 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications v supply = 15v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified parameter test conditions temp. (c) min typ max units input characteristics input offset voltage (notes 3, 14) 25 - 2 8 mv full - - 10 mv average input offset voltage drift full - 10 - v/c v io common mode rejection ratio (note 14) v cm = 10v 25 60 - - db full 50 - - db v io power supply rejection ratio (note 14) 4.5v v s 18v 25 64 - - db full 60 - - db non-inverting input (+in) current (note 14) 25 - 3 8 a full - - 20 a +in common mode rejection v cm = 10v 25 - - 0.1 a/v full - - 0.5 a/v +in power supply rejection 4.5v v s 18v 25 - - 0.06 a/v full - - 0.2 a/v inverting input (-in) current (note 14) 25 - 12 20 a full - 25 50 a -in common mode rejection v cm = 10v 25 - - 0.4 a/v full - - 0.5 a/v -in power supply rejection 4.5v v s 18v 25 - - 0.2 a/v full - - 0.5 a/v transfer characteristics transimpedance (notes 9, 14) 25 3500 - - v/ma full 1000 - - v/ma open loop dc voltage gain (note 9) r l = 400 ? , v out = 10v 25 70 - - db full 65 - - db open loop dc voltage gain r l = 100 ? , v out = 2.5v 25 60 - - db full 55 - - db ha-5020
4 fn2845.11 june 5, 2006 output characteristics output voltage swing (note 14) r l = 150 ? 25 to 85 12 12.7 - v -40 to 0 11 11.8 - v output current (guaranteed by output voltage test) 25 30 31.7 - ma full 27.5 - - ma power supply characteristics quiescent supply current (note 14) full - 7.5 10 ma supply current, disabled (note 14) disable = 0v full - 5 7.5 ma disable pin input current disable = 0v full - 1.0 1.5 ma minimum pin 8 current to disable (note 4) full 350 - - a maximum pin 8 current to enable (note 5) full - - 20 a ac characteristics (a v = +1) slew rate (note 6) 25 600 800 - v/ s full 500 700 - v/ s full power bandwidth (note 7) (guaranteed by slew rate test) 25 9.6 12.7 - mhz full 8.0 11.1 - mhz rise time (note 8) 25 - 5 - ns fall time (note 8) 25 - 5 - ns propagation delay (notes 8, 14) 25 - 6 - ns -3db bandwidth (note 14) v out = 100mv 25 - 100 - mhz settling time to 1% 10v output step 25 - 45 - ns settling time to 0.25% 10v output step 25 - 100 - ns ac characteristics (a v = +10, r f = 383 ? ) slew rate (notes 6, 9) 25 900 1100 - v/ s full 700 - - v/ s full power bandwidth (note 7) (guaranteed by slew rate test) 25 14.3 17.5 - mhz full 11.1 - - mhz rise time (note 8) 25 - 8 - ns fall time (note 8) 25 - 8 - ns propagation delay (notes 8, 14) 25 - 9 - ns -3db bandwidth v out = 100mv 25 - 60 - mhz settling time to 1% 10v output step 25 - 55 - ns settling time to 0.1% 10v output step 25 - 90 - ns intersil value added specifications input noise voltage (note 14) f = 1khz 25 - 4.5 - nv/ hz +input noise current (note 14) f = 1khz 25 - 2.5 - pa/ hz -input noise current (note 14) f = 1khz 25 - 25 - pa/ hz input common mode range full 10 12 - v -i bias adjust range (note 3) full 25 40 - a overshoot (note 14) 25 - 7 - % electrical specifications v supply = 15v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified (continued) parameter test conditions temp. (c) min typ max units ha-5020
5 fn2845.11 june 5, 2006 output current, short circuit (note 14) v in = 10v, v out = 0v full 50 65 - ma output current, disabled (note 14) disable = 0v, v out = 10v full - - 1 a output disable time (notes 10, 14) 25 - 10 - s output enable time (notes 11, 14) 25 - 200 - ns supply voltage range 25 5- 15 v output capacitance, disabled (note 12) disable = 0v 25 - 6 - pf video characteristics differential gain (notes 13, 14) r l = 150 ? 25 - 0.03 - % differential phase (notes 13, 14) r l = 150 ? 25 - 0.03 - gain flatness to 5mhz 25 - 0.1 - db electrical specifications v+ = +5v, v- = -5v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified. parameters are not tested. the limits are guarant eed based on lab characterizations, and reflect lot-to-lot variation. parameter test conditions temp. (c) min typ max units input characteristics input offset voltage (notes 3, 14) 25 - 2 8 mv full - - 10 mv average input offset voltage drift full - 10 - v/c v io common mode rejection ratio (notes 14, 15) 25 50 - - db full 35 - - db v io power supply rejection ratio (note 14) 3.5v v s 6.5v 25 55 - - db full 50 - - db non-inverting input (+in) current (note 14) 25 - 3 8 a full - - 20 a +in common mode rejection (note 15) 25 - - 0.1 a/v full - - 0.5 a/v +in power supply rejection 3.5v v s 6.5v 25 - - 0.06 a/v full - - 0.2 a/v inverting input (-in) current (note 14) 25 - 12 20 a full - 25 50 a -in common mode rejection (note 15) 25 - - 0.4 a/v full - - 0.5 a/v -in power supply rejection 3.5v v s 6.5v 25 - - 0.2 a/v full - - 0.5 a/v transfer characteristics transimpedance (notes 9, 14) 25 1000 - - v/ma full 850 - - v/ma open loop dc voltage gain r l = 400 ? , v out = 2.5v 25 65 - - db full 60 - - db electrical specifications v supply = 15v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified (continued) parameter test conditions temp. (c) min typ max units ha-5020
6 fn2845.11 june 5, 2006 open loop dc voltage gain r l = 100 ? , v out = 2.5v 25 50 - - db full 45 - - db output characteristics output voltage swing (note 14) 25 to 85 2.5 3.0 - v -40 to 0 2.5 3.0 - v output current (guaranteed by output voltage test) r l = 100 ? 25 16.6 20 - ma full 16.6 20 - ma power supply characteristics quiescent supply current (note 14) full - 7.5 10 ma supply current, disabled (note 14) disable = 0v full - 5 7.5 ma disable pin input current disable = 0v full - 1.0 1.5 ma minimum pin 8 current to disable (note 16) full 350 - - a maximum pin 8 current to enable (note 5) full - - 20 a ac characteristics (a v = +1) slew rate (note 17) 25 215 400 - v/ s full power bandwidth (note 18) 25 22 28 - mhz rise time (note 8) 25 - 6 - ns fall time (note 8) 25 - 6 - ns propagation delay (note 8) 25 - 6 - ns overshoot 25 - 4.5 - % -3db bandwidth (note 14) v out = 100mv 25 - 125 - mhz settling time to 1% 2v output step 25 - 50 - ns settling time to 0.25% 2v output step 25 - 75 - ns ac characteristics (a v = +2, r f = 681 ? ) slew rate (note 17) 25 - 475 - v/ s full power bandwidth (note 18) 25 - 26 - mhz rise time (note 8) 25 - 6 - ns fall time (note 8) 25 - 6 - ns propagation delay (note 8) 25 - 6 - ns overshoot 25 - 12 - % -3db bandwidth (note 14) v out = 100mv 25 - 95 - mhz settling time to 1% 2v output step 25 - 50 - ns settling time to 0.25% 2v output step 25 - 100 - ns ac characteristics (a v = +10, r f = 383 ? ) slew rate (note 17) 25 350 475 - v/ s full power bandwidth (note 18) 25 28 38 - mhz rise time (note 8) 25 - 8 - ns fall time (note 8) 25 - 9 - ns propagation delay (note 8) 25 - 9 - ns overshoot 25 - 1.8 - % electrical specifications v+ = +5v, v- = -5v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified. parameters are not tested. the limits are guarant eed based on lab characterizations, and reflect lot-to-lot variation. (continued) parameter test conditions temp. (c) min typ max units ha-5020
7 fn2845.11 june 5, 2006 -3db bandwidth (note 14) v out = 100mv 25 - 65 - mhz settling time to 1% 2v output step 25 - 75 - ns settling time to 0.25% 2v output step 25 - 130 - ns intersil value added specifications input noise voltage (note 14) f = 1khz 25 - 4.5 - nv/ hz +input noise current (note 14) f = 1khz 25 - 2.5 - pa/ hz -input noise current (note 14) f = 1khz 25 - 25 - pa/ hz input common mode range full 2.5v ? -v output current, short circuit v in = 2.5v, v out = 0v full 40 60 - ma output current, disabled (note 14) disable = 0v, v out = 2.5v, v in = 0v full - - 2 a output disable time (notes 14, 20) 25 - 40 - s output enable time (notes 14, 21) 25 - 40 - ns supply voltage range 25 5- 15 v output capacitance, disabled (note 19) disable = 0v 25 - 6 - pf video characteristics differential gain (notes 13, 14) r l = 150 ? 25 - 0.03 - % differential phase (notes 13, 14) r l = 150 ? 25 - 0.03 - gain flatness to 5mhz 25 - 0.1 - db notes: 2. suggested v os adjust circuit: the inverting input current (-i bias ) can be adjusted with an external 10k ? pot between pins 1 and 5, wiper connected to v+. since -i bias flows through the feedback resistor (r f ), the result is an adjustment in offset voltage. the amount of offset voltage adjustment is determined by the value of r f ( ? v os = ? -i bias *r f ). 3. r l = 100 ? , v in = 10v. this is the minimum current wh ich must be pulled out of the disable pin in order to disable the output. the output is considered disabled when -10mv v out +10mv. 4. v in = 0v. this is the maximum current that can be pulled out of the disable pin with the ha-5020 remaining enabled. the ha-5020 is considered disabled when the supply current has decreased by at least 0.5ma. 5. v out switches from -10v to +10v, or from +10v to -10v. specification is from the 25% to 75% points. 6. 7. r l = 100 ? , v out = 1v. measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay. 8. this parameter is not tested. the limits are guaranteed based on lab characterization, and refl ect lot-to-lot variation. 9. v in = +10v, disable = +15v to 0v. measured from the 50% point of disable to v out = 0v. 10. v in = +10v, disable = 0v to +15v. measured from the 50% point of disable to v out = 10v. 11. v in = 0v, force v out from 0v to 10v, t r = t f = 50ns. 12. measured with a vm700a video tester using a ntc-7 composite vits. 13. see ?typical performance curves? for more information. 14. v cm = 2.5v. at -40c product is tested at v cm = 2.25v because short test durat ion does not allow self heating. 15. r l = 100 ? . v in = 2.5v. this is the minimum current which must be pulled out of the disable pin in order to disable the output. the output is considered disabled when -10mv v out +10mv. 16. v out switches from -2v to +2v, or from +2v to -2 v. specification is from the 25% to 75% points. 17. fpbw = . 18. v in = 0v, force v out from 0v to 2.5v, t r = t f = 50ns. 19. v in = +2v, disable = +5v to 0v. measured from the 50% point of disable to v out = 0v. 20. v in = +2v, disable = 0v to +5v. measured from the 50% point of disable to v out = 2v. electrical specifications v+ = +5v, v- = -5v, r f = 1k ?, a v = +1, r l = 400 ?, c l 10pf, unless otherwise specified. parameters are not tested. the limits are guarant eed based on lab characterizations, and reflect lot-to-lot variation. (continued) parameter test conditions temp. (c) min typ max units fpbw slew rate 2 v peak -------------------------- - ;v peak = 10v. = slew rate 2 v peak -------------------------- - ;v peak =2v ha-5020
8 fn2845.11 june 5, 2006 test circuits and waveforms figure 1. test circuit for transimpedance measurements figure 2. small signal pulse response circuit figure 3. large signal pulse response circuit figure 4. small signal response f igure 5. large signal response + - 50 ? 50 ? dut hp4195 network analyzer v in v out r l r f , 1k ? 100 ? 50 ? + - dut v in v out r l r f , 681 ? 400 ? 50 ? + - dut r i 681 ? vertical scale: v in = 100mv/div., v out = 100mv/div. horizontal scale: 20ns/div. v in v out vertical scale: v in = 1v/div., v out = 1v/div. horizontal scale: 50ns/div. v in v out ha-5020
9 fn2845.11 june 5, 2006 schematic diagram r 2 800 r 5 2.5k r 6 15k d 2 q p2 r 1 60k q n1 r 3 6k q n2 d 1 q n3 q n4 r 4 800 r 7 15k dis q n7 r 9 820 q p4 q n6 q p3 r 8 1.25k q n5 +in q p7 r 13 1k r 12 280 q p6 q n8 q p5 r 10 820 q n9 q n11 q n10 q p10 q p8 q p9 r 11 1k r 14 280 q n14 r 16 400 r 22 280 q n16 r 17 280 r 18 280 q p11 r 15 400 r 19 400 q p14 q n12 q p12 -in q n13 q p13 c 2 r 23 400 r 26 200 r 24 140 r 20 140 q p15 c 1 q n17 r 25 20 q n18 r 25 140 r 21 140 r 26 200 q p16 r 27 200 r 33 2k q p18 q n20 q p17 r 28 20 q n15 r 30 7 q n19 o q n21 r 32 5 r 29 9.5 q p19 qp20 r 31 5 v+ v- q p1 r 33 800 1.4pf 1.4pf ha-5020
10 fn2845.11 june 5, 2006 application information optimum feedback resistor the plots of inverting and non-inverting frequency response illustrate the performance of the ha-5020 in various closed loop gain configurations. although the bandwidth dependency on closed loop gain isn?t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. this decrease may be minimized by taking advantage of the current feedback amplifier?s unique relationship between bandwidth and r f . all current feedback amplifiers require a feedback resistor, even for unity gain applications, and r f , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. thus, the amplifier?s bandwidth is inversely proportional to r f . the ha-5020 design is optimized for a 1000 ? r f at a gain of +1. decreasing r f in a unity gain application decreases stability, resulting in excessive peaking and overshoot. at higher gains the amplifier is more stable, so r f can be decreased in a trade-off of stability for bandwidth. the table below lists recommended r f values for various gains, and the expected bandwidth. pc board layout the frequency response of this amplifier depends greatly on the amount of care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended. if leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. attention must be given to decoupling the power supplies. a large value (10 f) tantalum or electrolytic capacitor in parallel with a small value (0.1 f) chip capacitor works well in most cases. a ground plane is strongly recommended to control noise. care must also be taken to minimize the capacitance to ground seen by the amplifier?s inverting input (-in). the larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. it is recommended that the ground plane be removed under traces connected to -in, and that connections to -in be kept as short as possible to minimize the capacitance from this node to ground. driving capacitive loads capacitive loads will degrade the amplifier?s phase margin resulting in frequency response peaking and possible oscillations. in most cases the oscillation can be avoided by placing an isolation resistor (r) in series with the output as shown in figure 6. the selection criteria for the isolation resistor is highly dependent on the load, but 27 ? has been determined to be a good starting value. enable/disable function when enabled the amplifier functions as a normal current feedback amplifier with all of the data in the electrical specifications table being valid and applicable. when disabled the amplifier output assumes a true high impedance state and the supply current is reduced significantly. the circuit shown in figure 7 is a simplified schematic of the enable/disable function. the large value resistors in series with the disable pin makes it appear as a current source to the driver. when the driver pulls this pin low current flows out of the pin and into the driver. this current, which may be as large as 350 a when external circuit and process variables are at their extremes, is requi red to insure that point ?a? achieves the proper potential to disable the output. the driver must have the compliance and capability of sinking all of this current. when v cc is +5v the disable pin may be driven with a dedicated ttl gate. the maximum low level output voltage of the ttl gate, 0.4v, has enough compliance to insure that the amplifier will always be disabled even though d 1 will not turn on, and the ttl gate will sink enough current to keep point ?a? at its proper voltage. when v cc is greater than +5v the disable pin should be driv en with an open collector device that has a breakdown rating greater than v cc . gain (a cl )r f ( ? ) bandwidth (mhz) -1 750 100 +1 1000 125 +2 681 95 +5 1000 52 +10 383 65 -10 750 22 v in v out c l r t + - r i r f r figure 6. placement of the output isolation resistor, r r 6 15k r 7 15k +v cc enable/ d 1 q p3 r 8 q p18 a r 33 r 10 disable input figure 7. simplified schematic of enable/disable function ha-5020
11 fn2845.11 june 5, 2006 referring to figure 7, it can be seen that r 6 will act as a pull-up resistor to +v cc if the disable pin is left open. in those cases where the enable/disable function is not required on all circuits some circuits can be permanently enabled by letting the disable pin float. if a driver is used to set the enable/disable level, be sure that the driver does not sink more than 20 a when the disable pin is at a high level. ttl gates, especially cmos versions, do not violate this criteria so it is permissible to control the enable/disable function with ttl. typical applications two channel video multiplexer referring to the amplifier u 1a in figure 8, r 1 terminates the cable in its characteristic impedance of 75 ? , and r 4 back terminates the cable in its characteristic impedance. the amplifier is set up in a gain configuration of +2 to yield an overall network gain of +1 when driving a double terminated cable. the value of r 3 can be changed if a different network gain is desired. r 5 holds the disable pin at ground thus inhibiting the amplifier until the switch, s 1 , is thrown to position 1. at position 1 the switch pulls the disable pin up to the plus supply rail thereby en abling the amplifier. since all of the actual signal switching takes place within the amplifier, it?s differential gain and phase parameters, which are 0.03% and 0.03 respectively, determine the circuit?s performance. the other circuit, u 1b , operates in a similar manner. when the plus supply rail is 5v the disable pin can be driven by a dedicated ttl gate as discussed earlier. if a multiplexer ic or its equivalent is used to select channels its logic must be break before make. when these conditions are satisfied the ha-5020 is often used as a remote video multiplexer, and the multiplexer may be extended by adding more amplifier ics. low impedance multiplexer two common problems surface when you try to multiplex multiple high speed signals into a low impedance source such as an a/d converter. the first problem is the low source impedance which tends to make amplifiers oscillate and causes gain errors. the second problem is the multiplexer which supplies no gain, introduces all kinds of distortion and limits the frequency response. using op amps which have an enable/disable function, such as the ha-5020, eliminates the multiplexer problems because the external mux chip is not needed, and the ha-5020 can drive low impedance (large capacitance) loads if a series isolation resistor is used. referring to figure 9, both inputs are terminated in their characteristic impedance; 75 ? is typical for video applications. since the drivers usually are terminated in their characteristic impedance the in put gain is 0.5, thus the amplifiers, u 2 , are configured in a gain of +2 to set the circuit gain equal to one. resistors r 2 and r 3 determine the amplifier gain, and if a different gain is desired r 2 should be changed according to the equation g = (1 + r 3 /r 2 ). r 3 sets the frequency response of the amplifier so you should refer to the manufacturers data sheet before changing its value. r 5 , c 1 and d 1 are an asymmetrical charge/discharge time circuit which configures u 1 as a break before make switch to prevent both amplifiers from being active simultaneously. if this design is extended to more channels the drive logic must be designed to be break before make. r 4 is enclosed in the feedback loop of the am plifier so that the large open loop amplifier gain of u 2 will present the load with a small closed loop output impedanc e while keeping the amplifier stable for all values of load capacitance. the circuit shown in figure 9 was tested for the full range of capacitor values with no oscillations being observed; thus, problem one has been solved. the frequency and gain characteristics of the circuit are now those of the amplifier and independent of any multiplexing action; thus, problem two has been solved. the multiplexer transition time is approximately 15 s with the component values shown. notes: 21. u 1 is ha-5020. 22. all resistors in ?. 23. s 1 is break before make. 24. use ground plane. video input #1 video input #2 r 1 75 r 3 681 r 2 681 r 4 75 r 5 2000 + - u 1a u 1b r 9 75 r 10 2000 r 7 681 r 8 681 r 6 75 +5v in +5v 0.1 f 10 f -5v in -5v 0.1 f 10 f + + 1 r 11 100 video output to 75 ? load +5v s 1 2 3 all off figure 8. two channel high impedance multiplexer ha-5020
12 fn2845.11 june 5, 2006 figure 8. low impedance multiplexer input b + - -5v + - +5v inhibit channel switch input a r 1a 75 r 1b 75 d 1a 1n4148 u 1c u 1a u 1b u 1d r 6 100k r 5a 2000 c 1a 0.047 f r 5b 2000 d 1b 1n4148 r 2a 681 r 3a 681 r 4a 27 0.01 f r 2b 681 r 4b 27 r 3b 681 0.01 f output u 2b u 2a c 1b 0.047 f notes: 25. u 2 : ha-5020. 26. u 1 : cd4011. typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified figure 9. input noise vs frequency (average of 18 units from 3 lots) figure 10. input offset voltage vs temperature (absolute value average of 30 units from 3 lots) figure 11. +input bias current vs temperature (average of 30 units from 3 lots) figure 12. -input bias current vs temperature (absolute value average of 30 units from 3 lots) frequency (hz) 10 100 1k 10k 100k 1 10 100 1 10 100 input noise voltage (nv/ hz ) a v = +10 -input noise current input noise voltage +input noise current temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 offset voltage (mv) 2 . 5 2.0 1.5 1.0 0.5 0.0 v supply = 15v v supply = 4.5v v supply = 10v temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 0 -0.5 -1.0 -1.5 -2.0 -2.5 v supply = 15v v supply = 4.5v v supply = 10v bias current ( a) temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 bias current ( a) 2.0 1.8 1.6 1.4 1.2 1.0 v supply = 15v v supply = 4.5v v supply = 10v ha-5020
13 fn2845.11 june 5, 2006 figure 13. transimpedance vs temperature (average of 30 units from 3 lots) figure 14. supply current vs supply voltage (average of 30 units from 3 lots) figure 15. disable supply current vs supply voltage (average of 30 units from 3 lots) figure 16. supply current vs disable input voltage figure 17. disable mode feedthrough vs frequency fig ure 18. disabled output leakage vs temperature (average of 30 units from 3 lots) typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified (continued) temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 open loop gain (m ? ) 6 5 4 3 2 1 v supply = 15v v supply = 4.5v v supply = 10v supply voltage ( v) 3 supply current (ma) 57 9111315 4 5 6 7 8 125 c 25 c -55 c supply voltage ( v) 3 supply current (ma) 57 9111315 0 4 5 6 7 125 c 25 c -55 c 1 2 3 disable = 0v disable input voltage (v) 135791113 15 supply current (ma) 5 4 3 2 1 0 6 7 8 9 v supply = 15v v supply = 4.5v v supply = 10v 0 -10 -20 -30 -40 -50 -60 -70 -80 feedthrough (db) 0 2m 4m 6m 8m 12m 14m 10m 16m 18m 20m frequency (hz) disable = 0v v in = 5v p-p r f = 750 ? temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 output leakage current ( a) 1.0 0.5 0 -0.5 -1.0 v out = +10v v out = -10v ha-5020
14 fn2845.11 june 5, 2006 figure 19. enable/disable time vs output voltage (average of 9 units from 3 lots) figure 20. non-inverting gain vs frequency figure 21. inverting frequency response figure 22. phase vs frequency figure 23. bandwidth and gain peaking vs load resistance figure 24. bandwidth and gain peaking vs feedback resistance typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified (continued) output voltage (v) -10-8-6-4-202468 10 enable time ( s) 2.0 1.6 1.2 0.8 0.4 0.0 1.8 1.4 1.0 0.6 0.2 disable time ( s) 20 16 12 8 4 0 18 14 10 6 2 enable time disable time frequency (hz) 0 24m 48m 72m 96m 120m -7 -6 -5 -4 -3 -2 -1 0 1 2 3 normalized gain (db) v out = 0.2v p-p c l = 10pf a v = +1 a v = +2 a v = +6 a v = +10 frequency (hz) 0 24m 48m 72m 96m 120m -7 -6 -5 -4 -3 -2 -1 0 1 2 normalized gain (db) v out = 0.2v p-p c l = 10pf a v = -1 a v = -2 a v = -6 a v = -10 r f = 750 ? -8 frequency (hz) 0 24m 48m 72m 96m 120m -225 -180 -135 -90 -45 0 +45 a v = -1 a v = -2 a v = -6 a v = -10 -270 -135 -90 -45 +45 +90 +135 +180 -180 0 inverting phase () non-inverting phase () a v = +1 a v = +2 a v = +6 a v = +10 load resistance ( ? ) -3db bandwidth (mhz) gain peaking (db) 0 200 400 600 800 1000 60 70 80 90 100 110 0 1 2 3 4 5 gain peaking -3db bandwidth c l = 10pf v out = 0.2v p-p feedback resistor ( ? ) 700 900 1.1k 1.3k 1.5k 85 90 95 100 105 0 5 10 15 20 -3db bandwidth (mhz) gain peaking (db) gain peaking -3db bandwidth c l = 10pf v out = 0.2v p-p ha-5020
15 fn2845.11 june 5, 2006 figure 25. bandwidth and gain peaking vs feedback resistance figure 26. bandwidth vs feedback resistance figure 27. rejection ratios vs temperature (average of 30 units from 3 lots) figure 28. rejection ratios vs frequency figure 29. output swing overhead vs temperature (average of 30 units from 3 lots) figure 30. output voltage swing vs load resistance typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified (continued) feedback resistor ( ? ) 400 600 800 1.0k 1.2k 80 85 90 95 100 -3db bandwidth (mhz) gain peaking -3db bandwidth c l = 10pf, a v = +2 v out = 0.2v p-p 0 5 10 15 20 gain peaking (db) feedback resistor ( ? ) 200 400 600 800 1000 40 50 60 70 80 -3db bandwidth (mhz) gain peaking = 0db c l = 10pf, a v = +10 v out = 0.2v p-p 30 20 10 temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 rejection ratio (db) 75 70 65 60 55 psrr cmrr frequency (hz) 10k 100k 1m 10m rejection ratio (db) -50 -60 -70 -80 -90 +psrr cmrr -40 -30 -20 -10 0 -psrr a v = +10 temperature ( c) output swing overhead ( v) 1.5 2.0 2.5 3.0 3.5 0 -20 -40 -60 80 100 120 140 60 40 20 v supply = 15v v supply = 4.5v v supply = 10v ( v supply ) - ( v out ) load resistance ( ? ) output voltage swing (v p-p ) 10 15 20 25 30 10k 1k 100 10 5 0 v supply = 15v v supply = 4.5v v supply = 10v ha-5020
16 fn2845.11 june 5, 2006 figure 31. short circuit current limit vs temperature figure 32. propagation delay vs temperature (average of 18 units from 3 lots) figure 33. propagation delay vs supply voltage (average of 18 units from 3 lots) figure 34. small signal overshoot vs load resistance figure 35. distortion vs frequency figure 36. differential gain vs supply voltage (average of 18 units from 3 lots) typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified (continued) temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 40 50 60 70 80 90 100 short circuit current (ma) -isc +isc temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 propagation delay (ns) 7.0 6.5 6.0 5.5 5.0 r load = 100 ? v out = 1v p-p supply voltage ( v) 3 5 7 9 11 13 15 5.0 6.0 7.0 8.0 9.0 10.0 11.0 propagation delay (ns) a v = +10 (r f = 383 ? ) r load = 100 ? v out = 1v p-p a v = +2 a v = +1 load resistance ( ? ) overshoot (%) 10 15 1000 800 600 0 5 0 400 200 v out = 100mv p-p , c l = 10pf v supply = 15v v supply = 5v a v = +2 a v = +1 a v = +1 a v = +2 frequency (hz) 1m 10m distortion (dbc) -50 -60 -70 -80 -90 hd2 v o = 2v p-p c l = 30pf hd3 hd3 (gen) hd2 (gen) 3 rd order imd 3 rd order imd (generator) supply voltage ( v) 3 5 7 9 11 13 15 differential gain (%) 0.01 0.02 0.03 0.04 0.05 0.06 0.07 r load = 1k r load = 150 ? r load = 75 ? frequency = 3.58mhz ha-5020
17 fn2845.11 june 5, 2006 figure 37. differential phase vs supply voltage (average of 18 units from 3 lots) figure 38. slew rate vs temperature (average of 30 units from 3 lots) typical performance curves v supply = 5v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25c, unless otherwise specified figure 39. non-inverting frequency respo nse figure 40. inverting frequency response figure 41. phase response as a function of frequency figure 42. bandwidth and gain peaking vs feedback resistance typical performance curves v supply = 15v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25 c , unless otherwise specified (continued) supply voltage ( v) 3 5 7 9 11 13 15 differential phase () 0.01 0.02 0.03 0.04 0.05 0.06 0.07 r load = 1k r load = 150 ? r load = 75 ? frequency = 3.58mhz 1200 1000 800 600 -60 slew rate (v/ s) -40 -20 0 20 40 60 80 100 120 140 + slew rate - slew rate v out = 20v p-p temperature ( c ) 5 4 3 2 1 0 -1 -2 -3 -4 -5 2m 10m 100m 200m frequency (hz) normalized gain (db) a v + 2 a v + 10 a v + 1 5 4 3 2 1 0 -1 -2 -3 -4 -5 2m 10m 100m 200m frequency (hz) normalized gain (db) a v = -1 a v = -2 a v = -10 5 4 3 2 1 0 -1 -2 -3 -4 -5 2m 10m 100m 200m frequency (hz) a v + 1 a v - 1 a v - 10 a v + 10 inverting phase () 180 135 90 45 0 -45 -90 -135 -180 non-inverting phase () feedback resistor ( ? ) 500 700 900 1100 1300 1500 140 130 120 10 5 0 -3db bandwidth (mhz) gain peaking (db) v out = 0.2v p-p c l = 10pf -3db bandwidth gain peaking a v = +1 ha-5020
18 fn2845.11 june 5, 2006 figure 43. bandwidth and gain peaking vs feedback resistance figure 44. bandwidth and gain peaking vs load resistance figure 45. bandwidth vs feedback resistance figure 46. rejection ratios vs frequency figure 47. propagation delay vs temperature figure 48. slew rate vs temperature typical performance curves v supply = 5v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25c, unless otherwise specified (continued) feedback resistor ( ? ) -3db bandwidth (mhz) gain peaking (db) 100 95 90 0 350 500 650 800 950 1100 -3db bandwidth gain peaking v out = 0.2v p-p c l = 10pf a v = +2 5 10 load resistor ( ? ) -3db bandwidth (mhz) gain peaking (db) 130 120 110 100 90 80 0 200 400 600 800 1000 6 4 2 0 v out = 0.2v p-p c l = 10pf -3db bandwidth gain peaking a v = +1 80 60 40 20 0 200 350 500 650 800 950 -3db bandwidth (mhz) feedback resistor ( ? ) v out = 0.2v p-p c l = 10pf a v = +10 frequency (hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 rejection ratio (db) 0.001m 0.01m 0.1m 1m 10m 30m a v = +1 cmrr positive psrr negative psrr temperature ( c) -50 -25 0 25 50 75 100 125 8.0 7.5 7.0 6.5 6.0 propagation delay (ns) r l = 100 ? v out = 1.0v p-p a v = +1 temperature ( c) -50 -25 0 25 50 75 100 125 500 450 400 350 300 250 200 150 100 slew rate (v/ s) v out = 2v p-p + slew rate - slew rate ha-5020
19 fn2845.11 june 5, 2006 figure 49. non-inverting gain flatness vs freque ncy figure 50. inverting gain flatness vs frequency figure 51. input noise characteristics figure 52. rejection ratio vs temperature figure 53. output swing vs temperature figure 54. enable/disable time vs output voltage typical performance curves v supply = 5v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25c, unless otherwise specified (continued) frequency (hz) 5m 10m 15m 20m 25m 30m 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 normalized gain (db) v out = 0.2v p-p c l = 10pf a v = +2, r f = 681 ? a v = +5, r f = 1 k ? a v = +1, r f = 1 k ? a v = 10, r f = 383 ? 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 normalized gain (db) frequency (hz) 5m 10m 15m 20m 25m 30m a v = -1 a v = -2 a v = -5 a v = -10 v out = 0.2v p-p c l = 10pf r f = 750 ? frequency (hz) 0.01k 0.1k 1k 10k 100k voltage noise (nv/ hz ) current noise (pa/ hz ) 100 80 60 40 20 0 1000 800 600 400 200 0 a v = 10, r f = 383 ? -input noise current +input noise current +input noise voltage 58 60 62 64 66 68 70 72 74 -100 -50 0 50 100 150 +psrr -psrr cmrr 200 250 temperature ( c) rejection ratio (db) 4.0 3.8 3.6 -60 -40 -20 0 40 60 80 100 120 140 20 temperature ( c) output swing (v) disable enable enable disable enable time (ns) 20 18 16 14 12 10 8 6 4 2 0 output voltage (v) -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 32 30 28 26 24 22 20 18 16 14 12 disable time ( s) ha-5020
20 fn2845.11 june 5, 2006 figure 55. disable feedthrough vs freque ncy figure 56. transimpedance vs frequency figure 57. transimpedence vs frequency typical performance curves v supply = 5v, a v = +1, r f = 1k ?, r l = 400 ?, t a = 25c, unless otherwise specified (continued) -20 -40 -50 -60 -70 -80 0.1m 1m 10m 20m feedthrough (db) frequency (hz) -30 -10 0 disable = 0v v in = 5v p-p r f = 750 ? -135 -90 -45 0 45 90 135 180 10 1 0.1 0.01 0.001 0.001m 0.01m 0.1m 1m 10m 100m phase angle () transimpedance (m ? ) r l = 100 ? frequency (hz) -135 -90 -45 0 45 90 135 180 10 1 0.1 0.01 0.001 0.001m 0.01m 0.1m 1m 10m 100m phase angle () r l = 400 ? frequency (hz) transimpedance (m ? ) ha-5020
21 fn2845.11 june 5, 2006 die characteristics metallization mask layout ha-5020 die dimensions: 1640 m x 1520 m x 483 m metallization: type: aluminum, 1% copper thickness: 16k ? 2k ? substrate potential (powered up): v- passivation: type: nitride over silox silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1k ? transistor count: 62 process: high frequency bipolar dielectric isolation 4 3 21 8 7 6 5 in+ in- out bal v- bal disable v+ ha-5020
22 fn2845.11 june 5, 2006 ha-5020 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.210 - 5.33 4 a1 0.015 - 0.39 -4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 -5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2845.11 june 5, 2006 ha-5020 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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